
Company Name: Mentor Graphics
Company Website: www.mentor.com
Company Profile: Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics. In 2004 it was ranked third in the EDA industry it helped create.
Job Location: Bangalore
Job Location: Bangalore
Job Role: Associate Application Engineer
Job Experience: Freshers
Job Eligibility: BE/BTech/ME/MTech Graduates
Job Summary:
Candidate should be a BE/BTech/ME/MTech Graduates from a recognized university
Job Description:
Familiar with VLSI design, HDL Synthesis, VLSI testing and design for testability.
Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred.
In-depth understanding of Design for Test (DFT) structures is required.
This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1).
Knowledge of scan data compression methodologies desired.
Operating Systems: UNIX, Linux, Sun Solaris.
Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.
CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan.
Familiarity with FastScan, FlexTest, LBISTArchitect, MBISTArchitect, and BSDArchitect a plus.
Strong trouble shooting skills and ability to break a complex problem into its components.
Excellent verbal and written communication skills.
Very self-motivated and results-oriented.
Travel maybe required.
Familiar with VLSI design, HDL Synthesis, VLSI testing and design for testability.
Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred.
In-depth understanding of Design for Test (DFT) structures is required.
This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1).
Knowledge of scan data compression methodologies desired.
Operating Systems: UNIX, Linux, Sun Solaris.
Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.
CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan.
Familiarity with FastScan, FlexTest, LBISTArchitect, MBISTArchitect, and BSDArchitect a plus.
Strong trouble shooting skills and ability to break a complex problem into its components.
Excellent verbal and written communication skills.
Very self-motivated and results-oriented.
Travel maybe required.
Job Skills:
Excellent Communication skills.
No comments:
Post a Comment